Creating UVM Tests Dynamically
Everyone who uses UVM knows that using the library ofter requires large amounts of boilerplate code. Tests are no exception.
Posts by Tag
- SystemVerilog 44
- UVM 16
- Software development 11
- e (IEEE 1647) 10
- vr_ad 7
- Fun and Games with CRV 5
- Coverage 4
- Musings on the verification process 3
- UVM_REG 3
- SVUnit 3
- Unit testing 3
- UVM RAL 2
- ABV 2
- Assertion Based Verification 2
- Formal Verification 1
SystemVerilog
A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1
I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic...
Favor Composition Over Inheritance - Even for Constraints
Simulation is currently the dominant functional verification technique, with constrained random verification the most widely used methodology. While producin...
Bigger Is Not Always Better: Builds Are Faster with Smaller Packages
One trend over the past few years is that the projects I've been working on tend to get bigger and more complicated. Bigger projects come with new challenges...
Testing SVA Properties and Sequences
After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. Wh...
Testing UVM Drivers, Part 2
In the previous post we looked at how we can emulate sequencer/driver communication using a lightweight stub of uvm_sequencer. Let's also look at some more t...
Testing UVM Drivers
It's that time again when I've started a new project at work. Since we're going to be using some new proprietary interfaces in this chip, this calls for some...
A Quick Look at SVAUnit
I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest...
The Humble Beginnings of a SystemVerilog Reflection API, Part 3
We've already looked at how to interrogate classes about what variables they have and how to set and get the values of these variables in different instances...
The Humble Beginnings of a SystemVerilog Reflection API, Part 2
In the previous post we saw that it's possible to use the Verilog Programming Interface (VPI) to programmatically get information about classes. For example,...
The Humble Beginnings of a SystemVerilog Reflection API
Reflection is a mechanism that allows "inspection of classes, interfaces, fields and methods at runtime without knowing the names of the interfaces, fields, ...
An Overview of UVM End-of-Test Mechanisms
A lot traffic coming from Google to the blog is from searches about setting the UVM drain time. That's because one of my first posts was about how to set the...
Registering Abstract Classes with the UVM Factory
Every now and again I stumble upon a situation where it's natural to use an abstract class. A typical example is when working with parameterized classes and ...
Packages, Class Names and UVM
Some time ago I wrote a post that challenged some of the established coding conventions of modern SystemVerilog. In particular, I expressed my displeasure wi...
Accessing Multiple Registers at Once
As I already mentioned, I gave a talk at DVCon Europe this year on how to implement burst accesses to memories modeled using UVM_REG. The motivation for that...
How Do I Transfer Thee? Let Me Count the Ways
I'll be giving a talk this week at DVCon Europe about how to use the UVM REG classes to verify memory sub-systems. In particular, I'll focus on how to transl...
Of Copies and Clones
Let's take a walk down memory lane and remember the fun times we had in college. For a few weeks at the end of the semester, though, things had to get seriou...
Be More Assertive about Your Testbench Code
Developing verification environments revolves around writing checks. We need to separate the concepts of checking the DUT from checking testbench code. DUT c...
My Take on SVA Usage with UVM
For verifying complex temporal behavior, SystemVerilog assertions (SVAs) are unmatched. They provide a powerful way to specify signal relationships over time...
On SystemVerilog Interface Polymorphism and Extendability
A state of the art SystemVerilog simulation environment consists of two separate worlds. There is the static world, where interface and modules (including th...
Rambling About UVM Factory Overrides - Per Instance
In the previous post we looked at how we can use the factory to direct an existing test by changing the type of sequence items that get created by that test'...
Rambling About UVM Factory Overrides - Per Type
When working with UVM, the phrase "you gotta use the factory!" gets drilled into our heads constantly. This is because in object oriented programming (OOP) e...
Even More Ideas on Coverage Extendability
In parts one and two of this series we looked at how to use policy classes to implement an extendable coverage model, where ignore bins can be tweaked. The f...
Some More Ideas on Coverage Extendability
In the previous post, we looked at how to use policy classes as parameters for a highly configurable coverage collector. This allows us to easily implement d...
Some Ideas on Coverage Extendability
The biggest advantage of e regarding coverage is, in my opinion, the ability to tweak the definitions of existing coverage groups by extending them from anyw...
Keeping Constraints and Covergroups in Sync
In the old days, people had to write all of their tests by hand. With chips getting bigger and bigger, it became clear that this painstaking process couldn't...
Fun and Games with CRV: Draw This Without Lifting Your Pencil
It's time for another installment in the "Fun and Games with CRV" series. I love doing these posts because there's something very engaging in modeling all so...
On SystemVerilog Coding Conventions - Challenging the Status Quo
When I first started out I remember reading all of these nice naming conventions for SystemVerilog. For example, when developing a new verification component...
Do You Want Sprinkles with That? - Mixing in Constraints
The goal of modern verification techniques is to do as much as possible with as little code as possible. This is best done with a "write once, tweak everywhe...
Patching a Leaky Boat - Handling UVM Bugs
This week I stumbled on an issue with the UVM base class library (BCL). I was using the register layer to access some memories and some things just didn't ad...
Fun and Games with CRV: The N-Queens Problem
It's been quite a while since we've solved the zebra puzzle using SystemVerilog. In this post we'll look at another oldie, but a goldie called the n-queens p...
A New Twist on SystemVerilog Enumerated Types
A well known SystemVerilog limitation is that the same literal cannot appear in more enumerated types within a package (or more precisely within a scope). L...
Fake It ‘til You Make It - Emulating Multiple Inheritance in SystemVerilog
In the last post I talked about interface classes and how they can be used to separate what an object "can" do from "how" it does it. While using interface c...
SystemVerilog 2012 Has Even More ‘Class’
While scouring the Web for blogs on verification, I came upon this post on Ankit Gopani's blog. He tries to shed some light on the various types of classes t...
Theory vs. Practice - Reserved Fields in UVM RAL
A seemingly simple question that comes up every now and then is "How do I properly handle reserved fields in UVM RAL?". The answer seems straightforward, rig...
Fun and Games with CRV: The Zebra Puzzle
The Zebra Puzzle is a classic logic puzzle, first published by Life International in 1962. Older versions of it exist and it is also sometimes called Einstei...
The Not So Comprehensive Guide to SystemVerilog Array Constraints
A few weeks back, during a late evening, I was writing some SystemVerilog code that was declaring constraints on arrays. My brain was already powering down a...
SystemVerilog Constraints from Above
After reading the title, some of you might be asking yourselves "What are constraints from above?". Constraints from above (CFAs) are an e term. As Reuven Na...
Temporary Variables in SystemVerilog Procedural Blocks
It is a well known fact that inside a procedural block variables can only be defined at the very beginning. Say you would have the following code: task some_...
Fun and Games with CRV: Sudoku
This week let's mix it up a bit and do something less work-related. Everybody probably knows what Sudoku is, but just in case you don't here's a link to the ...
UVM Drain Time - The Old Fashioned Way
One of the most useful additions of OVM 2.1 was the objection mechanism. You could raise an objection when starting your main traffic sequence and drop it on...
Custom Field Access Policies in UVM RAL
As promised in my last post today we're going to look at how to define a custom field access policy in the UVM register package. Let's use the same access po...
Keeping Your Constraints in One Basket
Doing constrained random verification is pretty easy on paper. You know what the transactions look like and what constraints you want to apply to their field...
A Subtle Gotcha When Using fork…join
I want to start things out light with a recent experience I've had using fork...join statements. My intention was to start several parallel threads inside a ...
UVM
Creating UVM Tests Dynamically
Everyone who uses UVM knows that using the library ofter requires large amounts of boilerplate code. Tests are no exception.
Favor Composition Over Inheritance - Even for Constraints
Simulation is currently the dominant functional verification technique, with constrained random verification the most widely used methodology. While producin...
An Overview of UVM End-of-Test Mechanisms
A lot traffic coming from Google to the blog is from searches about setting the UVM drain time. That's because one of my first posts was about how to set the...
Registering Abstract Classes with the UVM Factory
Every now and again I stumble upon a situation where it's natural to use an abstract class. A typical example is when working with parameterized classes and ...
Accessing Multiple Registers at Once
As I already mentioned, I gave a talk at DVCon Europe this year on how to implement burst accesses to memories modeled using UVM_REG. The motivation for that...
Of Copies and Clones
Let's take a walk down memory lane and remember the fun times we had in college. For a few weeks at the end of the semester, though, things had to get seriou...
My Take on SVA Usage with UVM
For verifying complex temporal behavior, SystemVerilog assertions (SVAs) are unmatched. They provide a powerful way to specify signal relationships over time...
Rambling About UVM Factory Overrides - Per Instance
In the previous post we looked at how we can use the factory to direct an existing test by changing the type of sequence items that get created by that test'...
Rambling About UVM Factory Overrides - Per Type
When working with UVM, the phrase "you gotta use the factory!" gets drilled into our heads constantly. This is because in object oriented programming (OOP) e...
Even More Ideas on Coverage Extendability
In parts one and two of this series we looked at how to use policy classes to implement an extendable coverage model, where ignore bins can be tweaked. The f...
Enum fields in UVM_REG
For some time now, I've been mulling over the problem of storing register field values as enumerations. Enumerations are a very handy tool to improve code re...
Do You Want Sprinkles with That? - Mixing in Constraints
The goal of modern verification techniques is to do as much as possible with as little code as possible. This is best done with a "write once, tweak everywhe...
Patching a Leaky Boat - Handling UVM Bugs
This week I stumbled on an issue with the UVM base class library (BCL). I was using the register layer to access some memories and some things just didn't ad...
Theory vs. Practice - Reserved Fields in UVM RAL
A seemingly simple question that comes up every now and then is "How do I properly handle reserved fields in UVM RAL?". The answer seems straightforward, rig...
UVM Drain Time - The Old Fashioned Way
One of the most useful additions of OVM 2.1 was the objection mechanism. You could raise an objection when starting your main traffic sequence and drop it on...
Custom Field Access Policies in UVM RAL
As promised in my last post today we're going to look at how to define a custom field access policy in the UVM register package. Let's use the same access po...
Software development
A Quick Look at SVAUnit
I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest...
The Humble Beginnings of a SystemVerilog Reflection API, Part 3
We've already looked at how to interrogate classes about what variables they have and how to set and get the values of these variables in different instances...
The Humble Beginnings of a SystemVerilog Reflection API, Part 2
In the previous post we saw that it's possible to use the Verilog Programming Interface (VPI) to programmatically get information about classes. For example,...
The Humble Beginnings of a SystemVerilog Reflection API
Reflection is a mechanism that allows "inspection of classes, interfaces, fields and methods at runtime without knowing the names of the interfaces, fields, ...
Packages, Class Names and UVM
Some time ago I wrote a post that challenged some of the established coding conventions of modern SystemVerilog. In particular, I expressed my displeasure wi...
Of Copies and Clones
Let's take a walk down memory lane and remember the fun times we had in college. For a few weeks at the end of the semester, though, things had to get seriou...
Be More Assertive about Your Testbench Code
Developing verification environments revolves around writing checks. We need to separate the concepts of checking the DUT from checking testbench code. DUT c...
Cooking at Home or Eating Out? - The Pros and Cons of Homegrown VIP
By now, we're all pretty much convinced that reuse is essential in the semiconductor industry. Gone are the days when we built everything from scratch an re-...
On SystemVerilog Coding Conventions - Challenging the Status Quo
When I first started out I remember reading all of these nice naming conventions for SystemVerilog. For example, when developing a new verification component...
A Quick Look at eUnit
Earlier this month I started a new project. I'm using Specman again, so this means you'll probably see more e related posts in the future. In a previous post...
A Quick Look at SVUnit
Some time back I, like other people before me, had the realization that doing verification is a lot like doing software programming. Modern hardware verifica...
e (IEEE 1647)
Fun and Games with CRV: Einstein’s Puzzle (Revisited)
Two weeks ago, Aurelian from AMIQ published a post on how to solve the so-called Einstein's puzzle using e. At the end, he challenged us readers to try and i...
vr_ad Twin Registers
In their quest to come up with ever more efficient architectures, concept engineers sometimes do crazy things. Twin registers (also called multiview register...
Experimental Cures for Flattened Register Definitions in vr_ad, Part 2
We've already talked about how to handle flattened register definitions from a modeling point of view in this post. This other post also showed us that acces...
Working with Multiple Instances of vr_ad Registers
The devices that we verify often have multiple instances of a certain register type. These registers are instantiated in a regular structure inside the desig...
Experimental Cures for Flattened Register Definitions in vr_ad
On my current project, I had an issue with my register definitions. Quite a few of my DUT's registers where just instances of the same register type. My vr_a...
Using indirect_access(…) in vr_ad
I've been working a lot with vr_ad lately. It has a lot of nice features for modeling registers, but unfortunately not all of them are documented. I'm going ...
A Quick Look at eUnit
Earlier this month I started a new project. I'm using Specman again, so this means you'll probably see more e related posts in the future. In a previous post...
Disabling Field Checks in vr_ad
Register packages are an awesome tool to easily implement checks on the behavior of our DUT by holding a copy of its state inside a register model. When ever...
“What are you implying?” - Overlapped Implication in e
A feature where SystemVerilog really shines for hardware verification is its assertion language. Making it easy to specify complex requirements in a clear an...
Custom Field Access Policies in vr_ad
A big part of verifying a design is checking its registers. A register packages is usually used to accomplish this task. It provides an abstract way of descr...
vr_ad
vr_ad Twin Registers
In their quest to come up with ever more efficient architectures, concept engineers sometimes do crazy things. Twin registers (also called multiview register...
Experimental Cures for Flattened Register Definitions in vr_ad, Part 2
We've already talked about how to handle flattened register definitions from a modeling point of view in this post. This other post also showed us that acces...
Working with Multiple Instances of vr_ad Registers
The devices that we verify often have multiple instances of a certain register type. These registers are instantiated in a regular structure inside the desig...
Experimental Cures for Flattened Register Definitions in vr_ad
On my current project, I had an issue with my register definitions. Quite a few of my DUT's registers where just instances of the same register type. My vr_a...
Using indirect_access(…) in vr_ad
I've been working a lot with vr_ad lately. It has a lot of nice features for modeling registers, but unfortunately not all of them are documented. I'm going ...
Disabling Field Checks in vr_ad
Register packages are an awesome tool to easily implement checks on the behavior of our DUT by holding a copy of its state inside a register model. When ever...
Custom Field Access Policies in vr_ad
A big part of verifying a design is checking its registers. A register packages is usually used to accomplish this task. It provides an abstract way of descr...
Fun and Games with CRV
Fun and Games with CRV: Einstein’s Puzzle (Revisited)
Two weeks ago, Aurelian from AMIQ published a post on how to solve the so-called Einstein's puzzle using e. At the end, he challenged us readers to try and i...
Fun and Games with CRV: Draw This Without Lifting Your Pencil
It's time for another installment in the "Fun and Games with CRV" series. I love doing these posts because there's something very engaging in modeling all so...
Fun and Games with CRV: The N-Queens Problem
It's been quite a while since we've solved the zebra puzzle using SystemVerilog. In this post we'll look at another oldie, but a goldie called the n-queens p...
Fun and Games with CRV: The Zebra Puzzle
The Zebra Puzzle is a classic logic puzzle, first published by Life International in 1962. Older versions of it exist and it is also sometimes called Einstei...
Fun and Games with CRV: Sudoku
This week let's mix it up a bit and do something less work-related. Everybody probably knows what Sudoku is, but just in case you don't here's a link to the ...
Coverage
Even More Ideas on Coverage Extendability
In parts one and two of this series we looked at how to use policy classes to implement an extendable coverage model, where ignore bins can be tweaked. The f...
Some More Ideas on Coverage Extendability
In the previous post, we looked at how to use policy classes as parameters for a highly configurable coverage collector. This allows us to easily implement d...
Some Ideas on Coverage Extendability
The biggest advantage of e regarding coverage is, in my opinion, the ability to tweak the definitions of existing coverage groups by extending them from anyw...
Keeping Constraints and Covergroups in Sync
In the old days, people had to write all of their tests by hand. With chips getting bigger and bigger, it became clear that this painstaking process couldn't...
Musings on the verification process
Cooking at Home or Eating Out? - The Pros and Cons of Homegrown VIP
By now, we're all pretty much convinced that reuse is essential in the semiconductor industry. Gone are the days when we built everything from scratch an re-...
Patching a Leaky Boat - Handling UVM Bugs
This week I stumbled on an issue with the UVM base class library (BCL). I was using the register layer to access some memories and some things just didn't ad...
Less Is More - Why I Favor Short Tests
We're not going to be looking at any code in this post. We are, however, going to examine the impact the length of the tests we write has on various aspects ...
UVM_REG
Accessing Multiple Registers at Once
As I already mentioned, I gave a talk at DVCon Europe this year on how to implement burst accesses to memories modeled using UVM_REG. The motivation for that...
How Do I Transfer Thee? Let Me Count the Ways
I'll be giving a talk this week at DVCon Europe about how to use the UVM REG classes to verify memory sub-systems. In particular, I'll focus on how to transl...
Enum fields in UVM_REG
For some time now, I've been mulling over the problem of storing register field values as enumerations. Enumerations are a very handy tool to improve code re...
SVUnit
Testing SVA Properties and Sequences
After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. Wh...
Testing UVM Drivers, Part 2
In the previous post we looked at how we can emulate sequencer/driver communication using a lightweight stub of uvm_sequencer. Let's also look at some more t...
Testing UVM Drivers
It's that time again when I've started a new project at work. Since we're going to be using some new proprietary interfaces in this chip, this calls for some...
Unit testing
Testing SVA Properties and Sequences
After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. Wh...
Testing UVM Drivers, Part 2
In the previous post we looked at how we can emulate sequencer/driver communication using a lightweight stub of uvm_sequencer. Let's also look at some more t...
Testing UVM Drivers
It's that time again when I've started a new project at work. Since we're going to be using some new proprietary interfaces in this chip, this calls for some...
UVM RAL
Theory vs. Practice - Reserved Fields in UVM RAL
A seemingly simple question that comes up every now and then is "How do I properly handle reserved fields in UVM RAL?". The answer seems straightforward, rig...
Custom Field Access Policies in UVM RAL
As promised in my last post today we're going to look at how to define a custom field access policy in the UVM register package. Let's use the same access po...
ABV
Testing SVA Properties and Sequences
After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. Wh...
My Take on SVA Usage with UVM
For verifying complex temporal behavior, SystemVerilog assertions (SVAs) are unmatched. They provide a powerful way to specify signal relationships over time...
Assertion Based Verification
Testing SVA Properties and Sequences
After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. Wh...
My Take on SVA Usage with UVM
For verifying complex temporal behavior, SystemVerilog assertions (SVAs) are unmatched. They provide a powerful way to specify signal relationships over time...
Formal Verification
A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1
I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic...