Custom Field Access Policies in UVM RAL

As promised in my last post today we're going to look at how to define a custom field access policy in the UVM register package.

Let's use the same access policy from last time: "writing to the field is allowed, except when trying to write the value 0; reading from the field is always allowed".

We'll start out by defining our register field class. The uvm_reg_field class provides a set of hook methods for developers to use when extending it. You might be tempted to think that we could use the pre_write() method in our case, but this will only work if we do implicit prediction (i.e. using calls to read() or write() inside our sequences). If we want to make it portable for cases when have traffic to our registers coming from other sources (such as legacy VIP or other DUT blocks when doing vertical reuse) we will want it to work for explicit prediction as well. To achieve this we have to extend the predict() method.

The uvm_reg_field class doesn't provide any pre-/post- hooks for the predict() method, but we can use callbacks for that. First we define our own callback class:

class vgm_wri0_cbs extends uvm_reg_cbs;

function new(string name = "vgm_wri0_cbs");;

virtual function void post_predict(input uvm_reg_field fld,
input uvm_reg_data_t previous,
inout uvm_reg_data_t value,
input uvm_predict_e kind,
input uvm_path_e path,
input uvm_reg_map map);
if (kind == UVM_PREDICT_WRITE && fld.get_access() == "RWI0" && value == 0)
value = previous;

We also have to declare our own register field class that defines the new RWI0 policy:

class vgm_rwi0_reg_field extends uvm_reg_field;

local static bit m_wri0 = define_access("RWI0");

function new(string name = "vgm_rwi0_reg_field");;

When declaring new access policies, it's best to use all uppercase characters as define_access(...) calls toupper() on the string we give it as an input argument and adds that to the table of access policies. What I would have liked to do at this point is create a callback object inside the constructor and add it to the field. This was unfortunately not possible as adding a callback does a call to get_full_name() which in turn requires a references to the field's parent register be set up. We have to postpone this step for higher up in the instance tree.

The last thing we need to do is declare the register:

class example_reg_type extends uvm_reg;

rand uvm_reg_field field1;
rand vgm_rwi0_reg_field field2;

function new(string name = "example_reg_type");, 32, UVM_NO_COVERAGE);

virtual function void build();
field1 = uvm_reg_field::type_id::create("field1");
field2 = vgm_rwi0_reg_field::type_id::create("field2");

field1.configure(this, 16, 16, "RW", 0, 0, 1, 1, 0);
field2.configure(this, 16, 0, "RWI0", 0, 0, 1, 1, 0);

// register callback
// - can't be done in vgm_rwi0_reg_field because it calls get_full_name()
// which requires the field's parent
vgm_wri0_cbs wri0_cbs = new("wri0_cbs");
uvm_reg_field_cb::add(field2, wri0_cbs);

We've defined field2 as being of type vgm_rwi0_reg_field and as having the RWI0 access policy. We've also added a callback to this field to actually implement the access policy.

This is the only way UVM RAL allows us to define custom field access policies and I can't say I'm particularly pleased about it. Using callbacks is slow and it is bloated. We've had to split our code into three sections: the callback class, the register field class and the register class). Had we have had a post_predict() hook in uvm_reg_field we could have just implemented everything inside our register field class, resulting in less lines of code and better encapsulation. This is definitely something I hope they will improve in a future release.

As usual, the code above including everything else needed to test it can be found on the blog's Sourceforge page.

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