Creating UVM Tests Dynamically
Everyone who uses UVM knows that using the library ofter requires large amounts of boilerplate code. Tests are no exception.
UVM
Favor Composition Over Inheritance - Even for Constraints
Simulation is currently the dominant functional verification technique, with constrained random verification the most widely used methodology. While producin...
An Overview of UVM End-of-Test Mechanisms
A lot traffic coming from Google to the blog is from searches about setting the UVM drain time. That's because one of my first posts was about how to set the...
Registering Abstract Classes with the UVM Factory
Every now and again I stumble upon a situation where it's natural to use an abstract class. A typical example is when working with parameterized classes and ...
Accessing Multiple Registers at Once
As I already mentioned, I gave a talk at DVCon Europe this year on how to implement burst accesses to memories modeled using UVM_REG. The motivation for that...
Of Copies and Clones
Let's take a walk down memory lane and remember the fun times we had in college. For a few weeks at the end of the semester, though, things had to get seriou...
My Take on SVA Usage with UVM
For verifying complex temporal behavior, SystemVerilog assertions (SVAs) are unmatched. They provide a powerful way to specify signal relationships over time...
Rambling About UVM Factory Overrides - Per Instance
In the previous post we looked at how we can use the factory to direct an existing test by changing the type of sequence items that get created by that test'...
Rambling About UVM Factory Overrides - Per Type
When working with UVM, the phrase "you gotta use the factory!" gets drilled into our heads constantly. This is because in object oriented programming (OOP) e...
Even More Ideas on Coverage Extendability
In parts one and two of this series we looked at how to use policy classes to implement an extendable coverage model, where ignore bins can be tweaked. The f...
Enum fields in UVM_REG
For some time now, I've been mulling over the problem of storing register field values as enumerations. Enumerations are a very handy tool to improve code re...
Do You Want Sprinkles with That? - Mixing in Constraints
The goal of modern verification techniques is to do as much as possible with as little code as possible. This is best done with a "write once, tweak everywhe...
Patching a Leaky Boat - Handling UVM Bugs
This week I stumbled on an issue with the UVM base class library (BCL). I was using the register layer to access some memories and some things just didn't ad...
Theory vs. Practice - Reserved Fields in UVM RAL
A seemingly simple question that comes up every now and then is "How do I properly handle reserved fields in UVM RAL?". The answer seems straightforward, rig...
UVM Drain Time - The Old Fashioned Way
One of the most useful additions of OVM 2.1 was the objection mechanism. You could raise an objection when starting your main traffic sequence and drop it on...
Custom Field Access Policies in UVM RAL
As promised in my last post today we're going to look at how to define a custom field access policy in the UVM register package. Let's use the same access po...