The Humble Beginnings of a SystemVerilog Reflection API, Part 3
We’ve already looked at how to interrogate classes about what variables they have and how to set and get the values of these variables in different instances...
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The Humble Beginnings of a SystemVerilog Reflection API, Part 2
In the previous post we saw that it’s possible to use the Verilog Programming Interface (VPI) to programmatically get information about classes. For example,...
The Humble Beginnings of a SystemVerilog Reflection API
Reflection is a mechanism that allows “inspection of classes, interfaces, fields and methods at runtime without knowing the names of the interfaces, fields, ...
An Overview of UVM End-of-Test Mechanisms
A lot traffic coming from Google to the blog is from searches about setting the UVM drain time. That’s because one of my first posts was about how to set the...
Registering Abstract Classes with the UVM Factory
Every now and again I stumble upon a situation where it’s natural to use an abstract class. A typical example is when working with parameterized classes and ...