Testing SVA Properties and Sequences
After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. Wh...
Recent Posts
Testing UVM Drivers, Part 2
In the previous post we looked at how we can emulate sequencer/driver communication using a lightweight stub of uvm_sequencer. Let's also look at some more t...
Testing UVM Drivers
It's that time again when I've started a new project at work. Since we're going to be using some new proprietary interfaces in this chip, this calls for some...
A Quick Look at SVAUnit
I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest...
The Humble Beginnings of a SystemVerilog Reflection API, Part 3
We've already looked at how to interrogate classes about what variables they have and how to set and get the values of these variables in different instances...