Bigger Is Not Always Better: Builds Are Faster with Smaller Packages
One trend over the past few years is that the projects I’ve been working on tend to get bigger and more complicated. Bigger projects come with new challenges...
Recent Posts
Testing SVA Properties and Sequences
After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. Wh...
Testing UVM Drivers, Part 2
In the previous post we looked at how we can emulate sequencer/driver communication using a lightweight stub of uvm_sequencer. Let’s also look at some more t...
Testing UVM Drivers
It’s that time again when I’ve started a new project at work. Since we’re going to be using some new proprietary interfaces in this chip, this calls for some...
A Quick Look at SVAUnit
I’ve been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest...