A Quick Look at SVAUnit
I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest...
I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest...
We've already looked at how to interrogate classes about what variables they have and how to set and get the values of these variables in different instances...
In the previous post we saw that it's possible to use the Verilog Programming Interface (VPI) to programmatically get information about classes. For example,...
Reflection is a mechanism that allows "inspection of classes, interfaces, fields and methods at runtime without knowing the names of the interfaces, fields, ...
Some time ago I wrote a post that challenged some of the established coding conventions of modern SystemVerilog. In particular, I expressed my displeasure wi...
Let's take a walk down memory lane and remember the fun times we had in college. For a few weeks at the end of the semester, though, things had to get seriou...
Developing verification environments revolves around writing checks. We need to separate the concepts of checking the DUT from checking testbench code. DUT c...
By now, we're all pretty much convinced that reuse is essential in the semiconductor industry. Gone are the days when we built everything from scratch an re-...
When I first started out I remember reading all of these nice naming conventions for SystemVerilog. For example, when developing a new verification component...
Earlier this month I started a new project. I'm using Specman again, so this means you'll probably see more e related posts in the future. In a previous post...
Some time back I, like other people before me, had the realization that doing verification is a lot like doing software programming. Modern hardware verifica...