Working with Multiple Instances of vr_ad Registers
The devices that we verify often have multiple instances of a certain register type. These registers are instantiated in a regular structure inside the desig...
Recent Posts
Experimental Cures for Flattened Register Definitions in vr_ad
On my current project, I had an issue with my register definitions. Quite a few of my DUT’s registers were just instances of the same register type. My vr_ad...
Using indirect_access(…) in vr_ad
I’ve been working a lot with vr_ad lately. It has a lot of nice features for modeling registers, but unfortunately not all of them are documented. I’m going ...
A New Twist on SystemVerilog Enumerated Types
A well known SystemVerilog limitation is that the same literal cannot appear in more enumerated types within a package (or more precisely within a scope).
Fake It ‘til You Make It - Emulating Multiple Inheritance in SystemVerilog
In the last post I talked about interface classes and how they can be used to separate what an object “can” do from “how” it does it. While using interface c...