My Take on SVA Usage with UVM
For verifying complex temporal behavior, SystemVerilog assertions (SVAs) are unmatched. They provide a powerful way to specify signal relationships over time...
Recent Posts
On SystemVerilog Interface Polymorphism and Extendability
A state of the art SystemVerilog simulation environment consists of two separate worlds. There is the static world, where interface and modules (including th...
Rambling About UVM Factory Overrides - Per Instance
In the previous post we looked at how we can use the factory to direct an existing test by changing the type of sequence items that get created by that test'...
Rambling About UVM Factory Overrides - Per Type
When working with UVM, the phrase "you gotta use the factory!" gets drilled into our heads constantly. This is because in object oriented programming (OOP) e...
Even More Ideas on Coverage Extendability
In parts one and two of this series we looked at how to use policy classes to implement an extendable coverage model, where ignore bins can be tweaked. The f...