Disabling Field Checks in vr_ad
Register packages are an awesome tool to easily implement checks on the behavior of our DUT by holding a copy of its state inside a register model. When ever...
Recent Posts
Temporary Variables in SystemVerilog Procedural Blocks
It is a well known fact that inside a procedural block variables can only be defined at the very beginning. Say you would have the following code: task some_...
A Quick Look at SVUnit
Some time back I, like other people before me, had the realization that doing verification is a lot like doing software programming. Modern hardware verifica...
Fun and Games with CRV: Sudoku
This week let's mix it up a bit and do something less work-related. Everybody probably knows what Sudoku is, but just in case you don't here's a link to the ...
“What are you implying?” - Overlapped Implication in e
A feature where SystemVerilog really shines for hardware verification is its assertion language. Making it easy to specify complex requirements in a clear an...