Temporary Variables in SystemVerilog Procedural Blocks

It is a well known fact that inside a procedural block variables can only be defined at the very beginning. Say you would have the following code:

task some_task();
  // do some stuff
  // ...
  
  // want to do some stuff here, but need a new var
endtask

You're writing some task, execute a few procedural statements and at some point you see that you need to add  new variable. You have to define that new variable way at the top (as the following code sample shows), far away from the point where it will be used, which doesn't really help with code readability. I find this to be a very arbitrary limitation.

task some_task();
  int some_var; // defined here, but used way farther down
  // doing some stuff
  // ...
  
  // do some stuff here with 'some_var'
endtask

Well, if you just need a temporary, throw-away variable, then you can just declare it and the statements operating on it inside a new begin-end sequential block:

task some_task();
  // do some stuff
  // ...
  
  begin
    int some_var;
    //do some stuff here with 'some_var'
  end
  
  // carry on with other statements
  // ...
endtask

While this is by no means a groundbreaking idea, it may help keep your code more understandable. Happy coding!