Saturday, March 8, 2014

Welcome to the Verification Gentleman Blog

My name is Tudor Timisescu. I am a Verification Engineer at Infineon Technologies, where I verify cryptographic co-processors and develop in house verification IP. While I mainly work with SystemVerilog and e, I also dabble in other topics such as formal verification, VPI applications, automation tools and more.

I started this blog to share my experiences as I learn about verification. I will be blogging about various problems I've encountered during my work and how I've solved them. I will also add tutorials on how to do cool stuff in UVM and I will post my thoughts on applying software development best practices to verification.

Feel free to use the blog's comments section to ask questions, post corrections or suggest new topics.

Stay tuned for my first technical post.


  1. Hi Timi,

    I've read your many posts in lots of forum like verification academy etc.,
    I've learned many things from your replies for people's queries. Thanks a lot for your effort to help lots of beginners.

    I've a query regarding writing constraint for AXI master address generation for below condition, it would be great if you give your comments!!!

    1. Address should be size aligned for any transefer
    2. Address should be Quad Word aligned if Data length is (<=) less than or equal to 2 Double
    Word (DW means 4 bytes here).
    3. And it should satisfy the below expression,
    Address[1:0] + (length * (2**burst_size)) <= 1 DW ---(for one DW transfer)
    Address[2:0] + (length * (2**burst_size)) <= 2 DW ---(for <= 2DW transfer)

    Please guide me to write constraints for these.!!